The semiconductor integrated circuit (IC) industry has experienced rapid growth. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs.
As semiconductor technologies further advance, a stacked IC device has emerged as an effective alternative to further reduce the physical size of a semiconductor device. In a stacked IC device, active circuits such as logic, memory, processor circuits and the like are fabricated on different semiconductor wafers. Two or more semiconductor wafers may be installed on top of one another to further reduce the form factor of the IC device. For example, two semiconductor wafers may be bonded together through suitable bonding techniques. One advantageous feature of a stacked IC device is that a higher density can be achieved. Although existing stacked semiconductor devices and methods of fabricating stacked IC devices have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects. Improvements in this area are desired.